In order to enable a high-speed access by CPU to operand data and a command, a cache memory is disposed between a work memory of large capacity and CPU. A set associative type cache memory (hereinafter referred to as “set associative type cache memory”, simply) has been used as a cache memory by which a relatively high cache hit rate can be achieved even with a relatively small circuit scale. A set associative type cache memory has a structure which allows different tags of data to be stored for the same cache entry. Supposing that the cache memory includes pairs of tag ways and data ways, and cache entries of those ways are composed of e.g. 256 kinds of entries, a cache entry of each way is selected according to a piece of index address information of low-order side 8 bits of a piece of address information. In a tag way, a piece of tag address information of more than one bit on a high-order side of the piece of index address information is stored as a cache tag for each cache entry indicated by an index address. In a data way, data of an address specified by corresponding index address information and tag address information are stored each cache entry indicated by an index address. In read access or write access by CPU, all of tag ways according to a piece of index address information of the access address are read; in case that the cache tag thus read matches with tag address information in the access address information, a corresponding cache entry of the data way which forms a pair with the tag way concerned will be made a target for an operation of the data read or data write. What is described here on a set associative type cache memory has been widely known.
As representatively described above, on a cache memory having a plurality of tag ways, a readout of cache tags from all of the tag ways at a time, and a quick judgment on the match or mismatch between a cache tag and a tag address are performed; in such case, the power consumption is increased because all the tag ways are activated in parallel. In this regard, an attempt is made to realize the reduction in power consumption by making possible to switch between a direct map format and a set associative format in Patent Document 1. In addition, in Patent Document 2, arrangement is made so that the division number of ways is set, and the ways are accessed in order, thereby eliminating the need for an action of parallel index to the ways.
Also, in regard to a cache memory, a bit inversion error (soft error) in which stored information thereof is undesirably inverted under the influence of cosmic rays (alpha rays, and beta rays) or the like can be caused. Such a bit inversion error can be detected by use of a parity bit. Especially, in Patent Document 3 in which a parity check is used, the need for a parity check circuit for each memory array is eliminated by performing a parity check on access address data, whereby an attempt to realize a lower power consumption by decrease in the number of parity check circuits is made.